In a digital data processing system such as a computer system or a network communication system, some specific digital data such as common parameters, control data or addresses are generally stored together in a designated data storage zone to be referred when required and to save storage space of the memory. The data format of the designated data storage zone can be an array for successively storing a plurality of data bytes.
Please refer to FIG. 1 which schematically shows the data storage zone 10 and three data bytes B11, B12 and B13 stored in the data storage zone 10. Each of the data bytes B11, B12 and B13 includes 8 bits, and thus there are 24 bits (numbers 0–23) stored in corresponding addresses (0)˜(23) in the data storage zone 10.
In practical, the 24 bits are divided into 5 columns 101˜105 for respectively storing 5 sets of different bit data. For example, there are four bits 0˜3 in the first column 101, six bits 4˜9 in the second column 102, seven bits 10˜16 in the third column 103, two bits 17˜18 in the fourth column 104, and five bits 19˜23 in the fifth column 105.
Since the digital processing system stores data byte by byte, the 5 sets of bit data in columns 101˜105 should be properly shifted and operated to be successfully accessed. For example,                Bit data in column 101=data byte B11 & 0x0F;        Bit data in column 102=((data byte B12 & 0x03)<<4)|((data byte B11 & 0xF0)>>4);        Bit data in column 103=((data byte B13 & 0x01)<<6)|((data byte B12 & 0xFC)>>2);        Bit data in column 104=(data byte B13 & 0x06)>>1; and        Bit data in column 105=(data byte B13 & 0xF8) 3;wherein each of the expressions “0x0F”, “0x03”,“0xF0”,“0x01”,“0xFC”, “0x06” and “0xF8” indicates an 8-bit hexadecimal mask data, the expression “X & Y” indicates an AND gate logic operation of X with Y, the expression “X|Y” indicates an OR gate logic operation of X with Y, the expression “X>>Y” indicates the rightward shift of the data X by Y bits and the expression “X<<Y” indicates the leftward shift of the data X by Y bits.        
In the above processing method, the mask data and shift amounts are preset and constant. When the bit specifications in the columns are rearranged, the mask data and shift amounts will be unable to be adjusted accordingly. Therefore, the bit data cannot be accessed correctly. Conventionally, these data have to be adjusted manually at the time the specification changes.
In order to solve this problem, the processing method is operated with bits as basic units in another prior art. Giving the five columns 101˜105 mentioned above as an example, the five columns 101˜105 are adjacent to one another, and respective bit numbers required by the five columns 101˜105 are determined. Afterwards, when the data in the columns are being accessed, the mask data and shift amounts are not required any longer. In stead, the bit ranges of the columns should be defined in advance, and then the columns are independently accessed. For example, the data storage zone 10 has a format of structural array, and the bit numbers of the sequentially adjacent columns 101˜105 are defined as follows:                Bit data in column 101 includes 4 bits;        Bit data in column 102 includes 6 bits;        Bit data in column 103 includes 7 bits;        Bit data in column 104 includes 2 bits; and        Bit data in column 105 includes 5 bits.        
This method, however, is performed logically. In practice, the digital processing system does not provide any real and continuous memory block for the bit data to be stored as immediately adjacent columns. The data, in stead, have to be stored according to the basic storage format of the system. For example, as shown in FIG. 2A, the basic storage format of the system is two bytes (16 bits) stored in corresponding addresses (0)˜(15) in the data storage zone 10. As described above, the bit data in columns 101, 102 and 103 are 4, 6, and 7 bits, respectively. Therefore, the storage of the bit data in the third column 103 is beyond the basic storage capacity, i.e. 16 bits. In other words, only the data in the first and the second columns can be stored in the same basic storage unit, e.g. the basic storage unit BX0, and the data in the other columns 103, 104 and 105 have to be stored in another 16-bit basic storage unit BX1. It is obvious that there will be 6-bit clearance between the column 102 and column 103, so the columns are not adjacent to each other. This might render errors in the subsequent accessing procedures.
Further, for different systems or platforms, their endians also differ from one another. Giving a system incorporating an 80×86 CPU as an example, the arrangement shown in FIG. 2B is referred to as “little endian”, i.e. the lower bit data are stored in lower bit addresses. In FIG. 2B, three basic storage units BL, BM and BH comprise bits 0˜7, 8˜15 and 16˜23 stored in addresses (0)˜(7), (8)˜(15) and (16)˜(23), respectively. On the other hand, the arrangement shown in FIG. 2C is referred to as “big endian”, i.e. the lower bit data are stored in higher bit addresses. In FIG. 2C, three basic storage units BL, BM and BH comprise bits 0˜7, 8˜15 and 16˜23 stored in addresses (16)˜(23), (8)˜(15) and (0)˜(7), respectively.
It is understood from the above description that different platforms, e.g. systems with different endians, requires different processing methods. Otherwise, the bit data will not be able to be correctly accessed.